Why does a working Arria 10 DDR3L design in the Quartus Prime software version 15.1.2 experience bit errors when it is upgraded to the Quartus Prime software version 16.0?

Description

In the Quartus® Prime software version 16.0, the DDR3L external memory controller default I/O settings changed from previous versions of the Quartus Prime software. The new settings can lead to fitter errors in the Quartus Prime software when overriding I/O assignments with settings in the Assignment Editor or in the QSF file, and they can also lead to signal integrity problems in hardware.

The default I/O settings in the Quartus Prime software version 15.1.2 are as follows:

• Address/Command: SSTL-135, 34 ohm with calibration output termination
• PLL Reference Clock: SSTL-135

The default I/O settings in the Quartus Prime software version 16.0 are as follows:

• Address/Command: SSTL-135 Class I, 12mA current strength
• PLL Reference Clock: LVDS with On-Chip termination

The Data bus default I/O settings did not change.

Resolution