Why do the out_refclk_fgt and out_system_pll_clk ports of the F-Tile Reference and System PLL Clocks Intel® FPGA IP fail to toggle when simulating the Intel Agilex® 7 F-Tile FPGA PHY IPs?

Description

The out_refclk_fgt and out_system_pll_clk ports of the F-Tile Reference and System PLL Clocks Intel® FPGA IP will not toggle in the simulation waveform. However, Intel Agilex® 7 F-Tile FPGA PHY IPs are still functional in simulation.

Resolution

There is currently no plan to fix this problem.