Why do the Low Latency 40-100GbE IP cores pass errored packets to the user interface during RX link down?

Description

Due to problem in logic implementation of Low Latency 40-100GbE IP core, when any lane is down there may be some erroneous packets passed to the user interface.

This happens because only the first 8 bits of the header "FB" (and not all 64 bits of header "FB555555555555D5") is looked at for preamble comparison, which triggers a valid SOP irrespective of whether the following 56 bits of header are correct or incorrect.

Resolution

This problem is fixed beginning with the Quartus® Prime software version 16.0.