Why do the Gen2 AN456 PCI Express High Performance Reference Designs have setup timing violations?

Description

You may see timing violations from and to the following nodes (setup and recovery).

*go_bit_r to *go_rcfg_r

*go_rcfg_rr to *ack_bit_r

These paths should be false.

Resolution

To work around this problem add the following constraints to the top level .sdc file:

set_false_path -from [get_registers *go_bit_r] -to [get_registers *go_rcfg_r]
set_false_path -from [get_registers *go_rcfg_rr] -to [get_registers *ack_bit_r]