Why do the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP not appear in the .pin file?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1 and earlier, the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP do not appear in the .pin file.

Resolution

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 18.1.1.