Knowledge Base Article

Why do memory reads and writes fail to my PCI Express Endpoint enabled BAR locations?

Description

Memory read and write transaction may fail if the PCI Express® Device Identification Class Code Register is set to 0.

A class code of 0 is reserved for devices built before class code definitions were finalized (pre PCI™ 2.0). Consequently, this is an invalid Device Class for PCI Express.

Resolution

You can obtain valid Device Class codes from the PCI-SIG® PCI Code and ID Assignment Specification.

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