Why do I see unexpected delays in Linux with designs using SDM-based SoC FPGAs and eASIC™ devices?

Description

The calculation performed within the arm-trusted-firmware code is based on an assumed fixed value of 400 MHz for the cs_at_clk.  However, designers can configure the cs_at_clk domain to be sourced by a clock frequency other than 400 MHz.  If this is done, then you may see unexpected delays in Linux.  This problem only impacts designs where the cs_at_clk is configured to be something other than 400 Mhz.

 

The following device families are impacted : 

• Stratix® 10 SoC FPGAs
• Agilex™ 7  SoC FPGAs
• Agilex™ 5 SoC FPGAs
• eASIC™ N5X Devices

Resolution

To remove the unexpected delays in Linux, change the following parameter in socfpga_plat_def.h file to match the frequency of cs_at_clk set in the HPS IP (See "CoreSight clock frequency" under HPS Clocks and resets -> Internal Clocks and Output Clocks)

 

#define PLAT_SYS_COUNTER_FREQ_IN_TICKS        (400000000) 

Stratix® 10 SoC FPGA  : https://github.com/altera-opensource/arm-trusted-firmware/blob/socfpga_v2.10.0/plat/intel/soc/stratix10/include/socfpga_plat_def.h#L99C9-L99C40

Agilex™ 7 SoC FPGA : https://github.com/altera-opensource/arm-trusted-firmware/blob/socfpga_v2.10.0/plat/intel/soc/agilex/include/socfpga_plat_def.h#L100

Agilex™ 5 SoC FPGA  : https://github.com/altera-opensource/arm-trusted-firmware/blob/socfpga_v2.10.0/plat/intel/soc/agilex5/include/socfpga_plat_def.h#L30

eASIC™ N5X Device: https://github.com/altera-opensource/arm-trusted-firmware/blob/socfpga_v2.10.0/plat/intel/soc/n5x/include/socfpga_plat_def.h#L99

 

This problem is scheduled to be fixed in a future release of arm-trusted-firmware.