Why do I see the HPS on Agilex™ SoC devices fail to boot, or observe some unexpected functional failures at run time?

Description

Due to a problem in the device manager firmware, you might fail to read/write certain RAMs on some Agilex™ AC.

You might observe the following HPS boot failures:

• HPS hangs at dcache memory write and read after executing the dcache_enable function in FSBL
• UART printout stops after “DDR: 8192 MiB”
• UART printout stops after “Loading Environment from MMC… ***”
• UART printout stops after “Verifying Hash Integrity … crc32”
• Various unexpected functional failures depending on the faulty RAM location

Resolution

To resolve this problem, update to the latest device manager firmware for the Quartus® Prime Pro Edition Software v21.2, 21.3, 21.4, 22.1, and 22.2. 

 

The latest device manager firmware is available from the following link: 

What is the latest device firmware for Agilex™ FPGA and Stratix® 10 FPGA devices?

 

This problem is fixed beginning with version 22.4 of the Quartus® Prime Pro Edition software.