Why do I see the "CLK 300027 Multiple clock assignment found" DRC error on the 25 MHz and 2.5 MHz clocks from the HPS GMII to RGMII Adapter IP?

Description

Due to a problem with the Quartus® Prime Pro Edition Software version 24.3.1 and earlier, you might see DRC violation "CLK 300027 Multiple clock assignment found" triggered by the HPS GMII to RGMII Adapter IP clocks "2_5M_2MUX1" and "25M_2MUX1" on the Agilex™ 5 FPGA devices.

This problem occurs specifically when the design includes more than one instance of the HPS GMII to RGMII Adapter IP.

Resolution

To work around this problem, on your SDC file, remove the "2_5M_2MUX1" and "25M_2MUX1" clocks and create unique clocks for each IP instance, as shown in this example:

 

remove_clock 2_5M_2MUX1

remove_clock 25M_2MUX1

 

create_generated_clock \

               -name clk2_5_mux1 \

               -source [get_pins hps|gmii_to_rgmii1|gmii_to_rgmii1|u_intel_gmii_to_rgmii_adapter_core|u_txclk_i_clock_mux|u_clk0_gate|outclk] \

               [get_pins hps|gmii_to_rgmii1|gmii_to_rgmii1|u_intel_gmii_to_rgmii_adapter_core|u_txclk_i_clock_mux|outclk|combout]

              

create_generated_clock \

               -name clk25_mux1 \

               -source [get_pins hps|gmii_to_rgmii1|gmii_to_rgmii1|u_intel_gmii_to_rgmii_adapter_core|u_txclk_i_clock_mux|u_clk1_gate|outclk] \

               [get_pins hps|gmii_to_rgmii1|gmii_to_rgmii1|u_intel_gmii_to_rgmii_adapter_core|u_txclk_i_clock_mux|outclk|combout] \

               -add

set_clock_groups -logically_exclusive -group clk2_5_mux1 -group clk25_mux1

 

create_generated_clock \

               -name clk2_5_mux0 \

               -source [get_pins hps|gmii_to_rgmii|gmii_to_rgmii|u_intel_gmii_to_rgmii_adapter_core|u_txclk_i_clock_mux|u_clk0_gate|outclk] \

               [get_pins hps|gmii_to_rgmii|gmii_to_rgmii|u_intel_gmii_to_rgmii_adapter_core|u_txclk_i_clock_mux|outclk|combout]

              

create_generated_clock \

               -name clk25_mux0 \

               -source [get_pins hps|gmii_to_rgmii|gmii_to_rgmii|u_intel_gmii_to_rgmii_adapter_core|u_txclk_i_clock_mux|u_clk1_gate|outclk] \

               [get_pins hps|gmii_to_rgmii|gmii_to_rgmii|u_intel_gmii_to_rgmii_adapter_core|u_txclk_i_clock_mux|outclk|combout] \

               -add

set_clock_groups -logically_exclusive -group clk2_5_mux0 -group clk25_mux0

 

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.