Why do I see the checker error during the simulation of Interlaken (2nd Generation) FPGA IP Design Example for VHDL variants targeting Agilex™ 7 FPGA devices with the ModelSim* - FPGA Edition SE 2023.4 or Questa*- FPGA Edition?

Description

You may see the following error message during the simulation of the Interlaken (2nd Generation) FPGA IP Design Example for VHDL variants targeting Agilex™ 7 FPGA devices with the ModelSim* - FPGA Edition SE 2023.4 or Questa*- FPGA Edition.

 

# ________________________________________________________________# 	 INFO: Start transmitting packets
# __________________________________________________________
# 
# 
# time:            329910000 checker error count          1
# __________________________________________________________
# 	 INFO: Stop transmitting packets
# __________________________________________________________
# 
# 
# __________________________________________________________
# 	 INFO: Checking packets statistics
# __________________________________________________________
# 
# 
# time:            344203333 checker error count         25
# 		 CRC24 errors reported:      0
# 		 SOPs transmitted:         100
# 		 EOPs transmitted:         100
# 		 SOPs received:            100
# 		 EOPs received:            100
# 		 ECC error count:            0
# __________________________________________________________
# 	 INFO: Test FAILED 
# 
# __________________________________________________________

Resolution

To work around this problem, please use ModelSim* - FPGA Edition SE 2023.2.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.