Why do I see Recovery timing violations from usr_rst_r to iopll_mac_clk in Intel Agilex® 7 devices when using PAM4 variants of the Interlaken IP Core (2nd Generation) Intel® FPGA IP?

Description

Due to a problem with the PAM4 implementation of the Interlaken IP Core (2nd Generation) Intel® FPGA IP, Recovery time timing closure violations may be seen from usr_rst_r to iopll_mac_clk in Intel Agilex® 7 devices in Intel® Quartus® Prime Pro Edition Software v19.2. This problem is due to a modeling issue that incorrectly assumes usr_rst_r to be synchronous with the IOPLL Reference Clock. The IOPLL User Guide states that the reset port is asynchronous to the reference clock.

Resolution

The recovery timing failure from usr_rst_r to iopll_mac_clk is false and can be safely ignored.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.