Why do I see recovery or removal timing violations on the automatically-created clock alt_cal_edge_detect_clk?

Description

Due to a problem in the Quartus® II software version 11.1 and earlier, a missing timing constraint on the clock alt_cal_edge_detect_clk in the transceiver logic may result in recovery and removal timing violations. The constraints for alt_cal_edge_detect_clk are automatically created by the Quartus II software.

Resolution

To work around this problem, add the following constraint to your Synopsys Design Constraints (.sdc) file:

set_clock_groups -asynchronous -group [get_clocks {alt_cal_edge_detect_clk}]

This problem is fixed beginning with the Quartus II software version 11.1 SP1.