Why do I see random read errors using DDR2 SDRAM Controller with UniPHY/ DDR3 SDRAM Controller with UniPHY or LPDDR2 SDRAM Controller with UniPHY?

Description

Due to a problem in the Quartus II software version 13.0sp1 and earlier, the output of DQS logic block may cause random read errors.

The following configurations may be affected:

• Arria® V: DDR3 and DDR3L SDRAM designs operating below 450 MHz
• Arria V: All supported operating frequencies for DDR2/LPDDR2 SDRAM
• Cyclone® V: All supported operating frequencies for DDR3/DDR3L/DDR2/LPDDR2 SDRAM

Resolution

This issue has been fixed with the Quartus II software version 13.0sp1 dp5 and later.

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• How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0 SP1?