Why do I see large routing wire delay added to my input and output paths resulting in timing violations?

Description

Due to an problem in the Quartus® II software versions 12.0 and 12.0 SP1, PLL compensation may be modeled incorrectly in the Fitter. This may result in large routing wire delay added to paths that cross clock domains such as input and output paths. This problem affects designs targeting Stratix® V, Arria® V, and Cyclone® V devices.

Resolution

This problem has been fixed in the Quartus II software version 12.0 SP2. To work around this problem, upgrade to the Quartus II software version 12.0 SP2.