Why do I see Hold timing violations in Intel Agilex® 7 FPGA devices when using PAM4 variants of the Interlaken IP Core (2nd Generation) Intel® FPGA IP?

Description

Due to a problem with the PAM4 implementation of the Interlaken IP Core (2nd Generation) Intel® FPGA IP, hold time timing closure violations may be seen in Intel Agilex® 7 FPGA devices in Intel® Quartus® Prime Pro Edition Software v19.2.

Resolution

A possible temporary workaround for this timing problem is to run seed sweeps so that better timing results are found.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.