Why do I see an error while trying to simulate the Max 10 ADC IP?

Description

Due to a problem in Quartus® Prime Standard Software, simulating the Intel® Max® 10 Analog to Digital Converter IP may cause the following error to show up.

In NCSim:

NCSim ADC simulation error- ncsim: *E,SYSFMT (/opt/intelFPGA/16.1/quartus/eda/sim_lib/cadence/fiftyfivenm_atoms_ncrypt.v): error

Resolution

Turn on the "Enable user created expected output file" option in the ADC Parameter editor and supply an input stimulus file. Do this for every channel that you have enabled.

For more details, refer to the User-Specified ADC Logic Simulation Output section in the ADC User guide.