Why do I see a one clock cycle delay difference between RTL and gate level simulation?

Description

Due to a problem in the Quartus® Prime software DSP register packing for V series devices, you may see a clock cycle delay difference on a register in gate level functional simulation compared to RTL functional simulation.

Resolution

To work around this problem either change fitter option "Auto Packed Registers" from "Auto" (default) to "Off" or download a patch for Quartus II software version 15.0.2

• Download the version 15.0.2 patch 2.15 for Windows (.exe)
• Download the version 15.0.2 patch 2.15 for Linux (.run)
• Download the Readme for the Quartus II software version 15.0.2 patch 2.15 (.txt)

This problem has been fixed beginning with version 15.1 Update 1 of the Quartus Prime software.