Why do I not read back the correct value from my PIO core generated by SOPC Builder?

Description

An issue has been identified that affects the generation of PIO cores with input ports of less than 8 bits. This issue only occurs when the project is configured for VHDL.

The issue results in the top bit of the first data byte for read being tied to logic 1.

To work around this issue, the user should mask the top bit of the first byte of the PIO in software when performing a read.

This issue shall be addressed in a later version of the Quartus® II tool.