Why do I get new data instead of dont care on my true dual port RAM in mixed port RDW in VCS simulation?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 18.1 and earlier, you may see new data instead of don't care behavior in mixed port RDW (Read during Write). This problem occurs on true dual port RAMs when running simulations on VCS.

Resolution

To work around this problem, either:

• run the simulation in ModelSim.
• run the simulation using the post fit netlist.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.