Why do I get logic contention errors when simulating the pci_mt32 MegaCore® in the QuartusTM software, with the Vector Waveform File (.vwf) provided with the function?

Description

You may get logic contention errors if you compile the design, which includes the PCI function using a third-party synthesis tool, with the Automatic I/O pad insertion option turned on. If this option is turned on, the bidirectional pins in the function do not get translated correctly in the EDIF or Verilog Quartus Mapper File (.vqm).

To disable the I/O pad insertion option, follow these steps:

Synplicity:

1. Choose on Select Device Options (Target menu).
2. Select the Disable I/O Insertion check box.

LeonardoSpectrum:

In the Optimize tab, uncheck the Add I/O pads option.

FPGA Compiler II/ FPGA Compiler II Altera Edition

1. Choose Create Implementation (Synthesis menu).
2. Select the Do not insert I/O Pads option.