Why do I get errors about SystemVerilog keywords when compiling Altera libraries for my third-party simulator?

Description

Reserved keywords in the SystemVerilog standard may be used in Altera's Verilog HDL simulation library files as identifiers such as module names or wire names. An example of such a word is "global" which is a reserved keyword in the IEEE 1800-2009 SystemVerilog standard, and is used as a module name in altera_primitives.v library file. Compiling such Verilog HDL library files in third-party simulators using a SystemVerilog option may result in compilation failures.

Altera recommends compiling all the library files with '.v' extension without using a SystemVerilog option, and also to compile all library files with '.sv' extension using SystemVerilog option. Refer to third-party simulator documentation for information on compiling HDL files with and without the SystemVerilog option.

An alternate solution is to use Altera's EDA Simulation Library Compiler to compile all Altera libraries for all the supported third-party simulators. For more details, please refer to Quartus II Handbook, Volume 3, Section I, Chapter 1 : Simulating Altera Designs, EDA Simulation Library Compiler (PDF).