Why do I get a System Error (SERROR) after I perform read-modify-write operations on the 32-bits ECC Peripheral registers?

Description

Due to an incorrect implementation of ECC Peripheral registers mapping, the ECC Peripheral registers listed below support read-modify-write operations for only bits [15:0]. Write operations on bits [31:16] will cause a System Error (SERROR). 

Agilex 5:

ECC Address Block Group:

• USBOTG0_ecc
• USB1_tx_ecc
• USB1_rx_ecc
• USB1_cache_ecc
• EMAC 0_tx_ecc
• EMAC 0_rx_ecc
• EMAC 1_tx_ecc
• EMAC1_rx_ecc
• EMAC2_tx_ecc
• EMAC2_rx_ecc
• OCRAM_ecc

Stratix 10 and Agilex 7:

ECC Address Block Group:

• EMAC0_rx_ecc
• EMAC0_tx_ecc
• EMAC1_rx_ecc
• EMAC1_tx_ecc
• EMAC2_rx_ecc
• EMAC2_tx_ecc
• USB0_ecc
• USB1_ecc
• NANDe_ecc
• NANDr_ecc
• NANDw_ecc
• SDMMC_ecc
• DMAC_ecc
• OnChip_RAM_ecc

SDRAML3Interconnect Address Block Group:

• hmc_adp_csr_ocp_slv_block
  • ECCCTRL1
  • ECCCTRL2
  • ERRINTEN
  • ERRINTENS
  • ERRINTENR
  • INTMODE
  • INTSTAT
  • DIAGINTTEST

Arria 10:

ECC Address Block Group:

• emac_rx_ecc
• emac_tx_ecc
• nandecc_ecc
• nandr_ecc
• nandw_ecc
• sdmcc_ecc
• onchip_ram_ecc
• dmac_ecc
• qspi_ecc
• usb_ecc
• usb_ecc
• nand_ecc

Resolution

The registers listed above only support read-modify-write operations for bits [15:0].