Why do I get a Fatal Error when I compile a design using an EDIF source file?

Description

Due to a problem in the Quartus® II software version 14.1 and later, you may get a Fatal Error when compiling an EDIF netlist.

Resolution

To work around this problem, generate a Verilog Quartus Mapping file (.vqm) from your 3rd party synthesis tool instead.

The problem is scheduled to be fixed in a future release of the Quartus II software.