Why do back to back read transactions to the Triple Speed Ethernet return incorrect data?

Description

"When using the Triple Speed Ethernet IP Core with multiple masters, and both masters attempt to read at the same time, the second transaction will return incorrect data."

There is an issue with the Triple Speed Ethernet IP core when back to back transactions occur. This problem will only be seen when multiple masters access this core. This issue will be fixed in a later version of the Quartus® II software.

The problem could be averted by placing a custom component in front of the Triple Speed Ethernet which would add a clock cycle delay between back to back transactions.