Why did the Timing report fail in the Agilex™ 7 FPGA M-Series External Memory Interface DDR4 DIMM Design Example?

Description

The following Lockstep DDR4 DIMM configurations may be unable to meet timing requirements: 

• DDR4 DIMM x64 
• DDR4 DIMM x64 + ECC 
• DDR4 DIMM x72 

Resolution

Please constrain the user clock to a small region, or if possible, lower the operating frequency. If these workarounds do not solve the Timing violation, please reach out to your Altera sales representative for further assistance.