Why did the LPDDR5 Agilex™ 7 FPGA M-Series EMIF IP Design Example fail simulation?

Description

Due to a problem in Quartus® Prime Pro Edition Software version 23.2,  you may see that the LPDDR5 example design has failed simulation in the Questa* FPGA Edition simulator.

The same design is passing simulation in the VCS* simulator.

Resolution

There is no workaround for this problem. 

This problem is fixed starting with the Quartus® Prime Pro Edition Software version 23.4