Why can't I constrain the timing path for the HPS SPI peripheral interface when routed to the FPGA fabric?

Description

Due to a problem in the Quartus® II software version 15.0, no timing paths are available to constrain the, Altera Arria® 5 and Cyclone® V SoC  SPI interface when routed to the FPGA.

Resolution

This issue is fixed in the Quartus II software from version 15.1.1.