Knowledge Base Article

Why can’t I place the bytes of two LVDS SERDES IP instances (in TX or Non-DPA RX modes) to the same IO sub-bank on Agilex™ 5 in Quartus® Prime Pro Edition Design Software versions prior to 25.3?

Description

Due to a problem in Quartus® Prime Pro Edition Design Software versions prior to 25.3, placing both LVDS SERDES IP instances within the same IO sub-bank may not be successful. If you attempt to put the bytes of both IP instances in the same IO sub-bank, you may encounter the following fitter error: 

Error(14996): The Fitter failed to find a legal placement for all periphery components. 
Resolution

This problem has been fixed in the Quartus® Prime Pro Edition Design Software Version 25.3. Use the Quartus Prime Pro Edition Design Software Version 25.3 to generate the LVDS SERDES IP and compile the project.  

If you must use the Quartus Prime Pro Edition Design Software versions prior to 25.3, please contact Support with this KDB link.

Related Articles

Can I distribute the channels of an Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO or Soft-CDR mode between two sub-banks? 

How many IOPLLs are used when implementing Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO/Soft-CDR mode and distributing the channels between two sub-banks? 

Published 30 days ago
Version 1.0
No CommentsBe the first to comment