Why are there recovery timing violations on the External Memory Interfaces Stratix® 10 FPGA IP for DDR4 reset_sync_pri_sdc_anchor signal?

Description

You might see recovery violations on the reset_sync_pri_sdc_anchor signal due to the automatic global promotion of this reset.

Resolution

To avoid the violations, apply the following assignment to prevent the signal from being promoted onto a global network:

set_instance_assignment -name GLOBAL_SIGNAL OFF -to <hierarchy>|reset_sync_pri_sdc_anchor