Why are there hold violations on my PHYLite design?

Description

Due to a problem in the Quartus® Prime Standard Edition software version 17.0 Update 2 and earlier, you may see hold time violations on clocks connected to <group_1_strobe_out> output pin.

You will also notice the Warning message below in Fitter report to confirm this problem.

Warning(332087): The master clock for this clock assignment could not be derived.  Clock: <pin connected to group_1_strobe_out> was not created.

Resolution

To work around this problem, update the following two constraints in PHYLite SDC file <*_altera_phylite_arch_nf_*.sdc>.

set write_fifo_clk [get_keepers -nowarn ${inst}*|core|arch_inst|group_gen[$i_grp_idx].u_phylite_group_tile_20|lane_gen[*].u_lane*~out_phy_reg]

set write_fifo_clk_neg [get_keepers -nowarn ${inst}*|core|arch_inst|group_gen[$i_grp_idx].u_phylite_group_tile_20|lane_gen[*].u_lane*~out_phy_reg__nff]

This problem is fixed beginning with the Quartus Prime Standard Edition software version 17.1