Knowledge Base Article

Why are the stable and resolution valid bits within the Status register of the Clocked Video Input II Intel® FPGA IP stuck at 0?

Description

Due to a problem with the Clocked Video Input II (4K Ready) Intel® FPGA IP in Intel® Quartus® Prime Software version 17.0 software, you may observe the above problem if you are using embedded synchronization mode.

Resolution

There is no workaround for this problem.

Updated 25 days ago
Version 3.0
arria® 10 fpgas and socs
arria® ii fpgas
arria® v fpgas and socs
cyclone® 10 lp fpga
cyclone® iv fpgas
cyclone® v fpgas and socs
fpga dev tools quartus® prime software pro
fpga dev tools quartus® prime software standard
stratix® iv fpgas
stratix® v fpgas
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