Why are the Frame Buffer II IP core dout_data, master_wr_writedata and master_rd_readata signals shown as unknown during simulation?

Description

Due to a problem in the Quartus® Prime software version 15.1, you may observe the Frame Buffer II IP core dout_data, master_wr_writedata and master_rd_readata signals showing as unknown during simulation. Hardware operation is not affected.

Resolution

This problem is fixed beginning with the Quartus Prime software version 16.0.