Why are the clock constraints for ALTPLL incorrect when using derive_pll_clocks?

Description

Due to a problem in the Quartus® Prime software version 16.0 and 16.0 Update 1, you may see that the phase value is incorrect in the constraints generated by derive_pll_clocks. This occurs when using the ALTPLL IP.

Resolution

This problem is fixed beginning with the Quartus Prime software version 16.0 Update 2.