Knowledge Base Article

Why are the Arria 10 DDR4 Mode Register 4 (MR4) write/read preamble bits set incorrectly?

Description
There is a known issue in the Quartus® II software version 13.1 Arria 10 Edition where the DDR4 MR4 write/read preamble bits are set incorrectly.
Resolution
The issue is fixed in the Quartus II software version 14.0 Arria 10 Edition.
Updated 2 months ago
Version 2.0
arria® 10 fpgas and socs
FPGA Dev Tools Quartus II Software
troubleshooting
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