Why are the Altera_PLL output clocks stuck low when simulating this megafunction in Cadence NCSim?

Description

If you are using NCSim to simulate the Altera_PLL megafunction, some of the output clocks may be stuck low.

Resolution

There are two workarounds for this issue:

1. To instantiate Altera_PLL, check "Enable physical output parameters" in the megafunction, and set the parameters accordingly to get the clocks you want.

2. Enable the macro SIM_USE_ICD_PLL_RECONFIG_MODEL to use the physical simulation model as shown below for Cyclone® V devices.  You will need to edit the commands below when targeting Arria® V or Stratix® V devices.

 ncvlog -DEFINE SIM_USE_ICD_PLL_RECONFIG_MODEL=TRUE "/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver

This issue is fixed starting in the Quartus® II software version 13.1.