Why are the Agilex™ 7 PLLs not meeting the Datasheet Specification for the Time Required To Lock From End-of-Device Configuration or deassertion of reset?

Description

In Agilex™ 7 FPGAs and SoCs Device Data Sheet, Table 30 shows the I/O PLL specification for time required to lock from end-of-device configuration or deassertion of reset, tLOCK to be 1ms. The duration should be measured starting from the assertion of the init_done pin or the deassertion of the areset signal, up to the assertion of the lock signal of a single I/O PLL. Please be aware that this specification is intended for standalone PLLs and does not account for design complexity.

Resolution

No workaround is needed, as this is just to clarify the datasheet information further.