Why are Questa*-Intel® FPGA Edition software and ModelSim*-Intel® FPGA Edition software VHDL simulations failing for GTS Ethernet Hard IP designs with Auto-Negotiation and Link Training (AN/LT) enabled?

Description

Due to a problem in the Quartus® Prime Pro Edition Software versions 24.3 and 24.3.1, Questa*-Intel® FPGA Edition software and ModelSim*-Intel® FPGA Edition software VHDL simulation failures may occur for GTS Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled designs.

Resolution

To work around this problem in the Quartus® Prime Pro Edition Software versions 24.3 and 24.3.1, navigate to the “<design_example_dir>/example_testbench” folder and add the following command in the Testbench file ‘basic_avl_tb_top.sv’

initial begin

force   basic_avl_tb_top.intel_eth_gts_hw.IP_INST[0].hw_ip_top.dut.intel_eth_gts_0.hip_inst.n_channel_superset_wrapper_inst.n_channel_superset.hal_top_wrapper_inst.hal_top_ip.shared_hal_coreip_inst_0.mc_inst.x_std_ipfluxtop_flux_core_shim_wrap_0.sf_rtl_ncrypt_inst.sf_rtl_inst.iflux_ingress_direct_lane0[231] = 0;

end 

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.1.