Why are Qsys components removed during synthesis or fail in simulation?

Description

Due to a problem in the Quaruts® II software version 11.1 SP2 and earlier, components in your Qsys design may be incorrectly connected and removed during synthesis if greater than 63 slave interfaces connect to a single master interface. RTL simulation with code generated by Qsys may also fail because transactions do not reach the component.

Resolution

To work around this problem, reduce the number of slave interfaces connected directly to a master. You can use a bridge to group some components with slave interfaces and connect the bridge to the master interface.

This issue is fixed beginning with the Quartus II software version 12.0.