Why are my output pins not recognized in Quartus® Pin Planner after Analysis & Synthesis?

Description

Due to a problem in Quartus® Prime Pro Edition Software version 23.3 and later, output signals without wire assignments in Verilog HDL are not recognized by Pin Planner after Analysis & Synthesis. In earlier versions of Quartus® Prime Pro Edition Software, wire assignments were not required.

Resolution

This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software.