Why are errored packets (FCS errors, runts, fragments) observed using the F-Tile Ethernet FPGA Hard IP?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and later, asserting the force_rf register bit may cause the F-Tile Ethernet Altera® FPGA Hard IP to start transmitting errored packets.

Resolution

To work around this problem, if the link partner sees an errored packet, assert the tx_reset on the F-Tile Ethernet Altera® FPGA Hard IP.
There is no fix for this problem.