Why are AXI Interface Ready-Valid Latency parameters of Content-Addressable Memory FPGA IP within the Memory Subsystem FPGA IP disabled?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the parameters under the AXI Interface Ready-Valid Latency section are disabled in the Content-Addressable Memory FPGA IP.

Resolution

This problem has been fixed in the Quartus® Prime Pro Edition Software version 23.4.