Knowledge Base Article

Why am I seeing a difference in the option of number of chip selects for DDR3 UniPHY IP generated in Quartus II V12.0 and V13.0 and later versions?

Description
The behaviour of DDR3 IP generated in QII V12.0 is incorrect. The number of chip select option for DDR3 UniPHY controller is limited to 2 for both Arria V and Cyclone V device.
Resolution
This issue has been fixed in QII V13.0
Updated 2 months ago
Version 2.0
arria® v fpgas and socs
FPGA Dev Tools Quartus II Software
troubleshooting
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