Which Triple Speed Ethernet (TSE) MAC registers must be set to run a simulation?

Description

To configure the Altera® Triple Speed Ethernet (TSE) MegaCore® function for simulation, you need to set the MAC and PCS registers according to the table below.

Please take note that command_config register should be the last register written because TSE operation will start when TX_EN and RX _EN in the command_config register are set. The order that the other registers are configured is not critical.

Registers in bold are basically required configurations for TSE MAC and PCS respectively to start its operation.

Table 1: MAC registers

Register Offset	Register Name	Value	Notes
0x08	command_config	0x400003B	transmit and receive paths enabled, gigabit ethernet enabled, promiscuous mode enabled, RX frame padding removal enabled, RX erroneous frame discard enabled
0x04	scratch	0xAAAAAAAA	N/A
0x0C	mac_0	0x17231C00	MAC address of 0x001C23174ACB
0x10	mac_1	0x0000CB4A	MAC address of 0x001C23174ACB
0x14	frame_length	0x533	Maximum frame length of 1518 bytes
0x18	pause_quant	0x0f	N/A
0x1C	RX_section_empty	0x10	N/A
0x20	RX_section_full	0x10	N/A
0x24	TX_section_empty	0x10	N/A
0x28	TX_section_full	0x10	N/A
0x2C	RX_almost_empty	0x08	N/A
0x30	RX_almost_full	0x08	N/A
0x34	TX_almost_empty	0x08	N/A
0x38	TX_almost_full	0x0A	N/A

Table 2: PCS registers

Register Offset	Register Name	Value	Notes
0x00	PCS control	0x00000000	No features enabled
0x20	scratch	0x0000AAAA	N/A
0x28	if_mode	0x00000009	Enable SGMII, SGMII speed - gigabit