Which index of the fclk[1..0] and loaden[1..] signals should I use when implementing a multi-bank, wide TX interface using the Stratix 10 Altera LVDS SERDES IP in external pll mode?

Description

For multi-bank wide TX configurations with external pll using Stratix® 10 device LVDS IP, only the second pair of clocks from the external pll (pair indexed by [1]) are valid

Resolution

This will be updated in the next version of the Intel® Stratix 10 device High-Speed LVDS I/O User Guide