Which clock edge is used to launch or capture Active Serial (AS) signals in the Serial Flash Loader (SFL) IP ?

Description

When programming a Serial Configuration (EPCS) device, a Quad-Serial Configuration (EPCQ) device or an EPCQ-L Serial Configuration device using the Serial Flash Loader (SFL) IP, Active Serial (AS) signals from/to the FPGA are launched or captured at the following clock edge: 

• nCS and ASDO (DATA0) from the FPGA are launched on the falling edge of DCLK.
• DATA (DATA1) to the FPGA is captured on the rising edge of DCLK.

For the overall timing relationship for AS configuration, refer to the respective device handbook or device datasheet.