When using the R-Tile Avalon® Streaming FPGA IP for PCI Express, can the tx_st_ready_o signal be utilized to ensure enough credits are available to send a TLP?

Description

When using the R-Tile Avalon® Streaming FPGA IP for PCI Express, the tx_st_ready_o signal cannot be utilized to ensure enough credits are available to send a transaction layer protocol (TLP).

The tx_st_ready_o signal of the R-Tile Avalon® Streaming FPGA IP for PCI Express is not dependent on any credit checking logic. The credit checking logic needs to be implemented in user logic utilizing the TX Flow Control Interface.

The tx_st_ready_o signal of the R-Tile Avalon® Streaming FPGA IP for PCI Express can be deasserted for any of the following conditions:

• The LTSSM is not ready.
• A retry is in progress.
• The R-Tile Avalon Streaming IP is busy sending internally generated TLPs.
• The internal R-Tile TX FIFO is full.

Resolution

This updated information has been added to version 22.1 5.0. release of Table 55. Avalon Streaming TX Interface Signals in the R-tile Avalon® Streaming FPGA IP for PCI Express User Guide.