When using the Arria V GZ and Stratix V Hard IP for PCI Express in multiple packets per cycle mode, why are the signals rx_st_bardec2 and rx_st_bar2 not created?

Description

Due to a problem in the IP generation, these signals are not automatically exported when mutliple packets per cycle is checked.

Resolution

Export the signals rx_st_bardec2 in altpcie_sv_hip_ast_hwtcl.v to the top level output of rx_st_bar2 when using multiple packets per cycle, as shown below:

output [7:0] rx_st_bar2,

assign rx_st_bar2       =  rx_st_bardec2[7:0];

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