What is the minimum pulse width for the Hard Processor System cold and warm resets (nPOR, nRST) in Cyclone® V devices?

Description

The minimum pulse width for the Hard Processor System cold and warm resets (nPOR, nRST)  is 6 oscillator 1 (osc1) clock cycles on Cyclone® V devices. The osc1 clock range is 10 - 50 MHz.

Resolution

This information will be added to the next version of the Cyclone® V handbook.