What is the Frequency of the HPS Clocks connected to the FPGA during FPGA Boot before the preloader has run?

Description

On Cyclone® V and Arria® V SOC devices, if BSEL is set to FPGA boot or CSEL= 00, the PLLs are in bypass mode.  The HPS user clocks exported to the FPGA fabric will run at OSC1 Frequency until the PLLs are configured (normally by the Preloader).

Resolution

This information is fixed starting with version 15.1 of the Cyclone® V and Arria® V Device Handbooks.