What is the fast read timing information for serial configuration devices (EPCS)?

Symbol

Parameter

Min

Max

Unit

fRCLK

Read clock frequency (from FPGA or embedded processor) for read bytes operation

—

20

MHz

fCLK

Fast Read clock frequency

—

40

MHz

tCH

DCLK high time

11

—

ns

tCL

DCLK low time

11

—

ns

tODIS

Output disable time after read

—

8

ns

tnCLK2D

Clock falling edge to data

—

8

ns